The invention is in the field of VLSIC microcircuits, and particularly concerns the use of shift register latches (SRL's) to test and evaluate the circuitry in a VLSI micro circuit. In particular, this invention relates to the use of boundary scanning registers which are integrated into the structure of a microcircuit for the purpose of scan-testing the input and output cells of the microcircuit.
During the commercial production of integrated circuits, some defective devices are unavoidably produced. These need to be identified and sorted out so that only the good devices are mounted in physical supports such as dual in-line packages. After the wafer fabrication is completed, each finished wafer undergoes a wafer-sort process where each die on the wafer is electrically tested using miniaturized probes that touch contact pads formed on the die.
With the advent of VLSIC's having large numbers of pads, it has become impractical to contact each and every pad. Therefore, boundary scan methods such as LSSD have been used to apply input signals or stimulus, and to read the output signals, using a small subset of the available pads. However, such methods do not test the part of an integrated circuit which is outside of the boundary scan, namely, the input and output pads and the input and output buffers. Boundary scan methods could be extended to include this circuitry, but this results in several disadvantages. The test signal levels are different and thus translator circuits are required, which add cost and consume die area. These translator circuits must be disabled during normal operation of the integrated circuit, and this requires additional circuitry. Other approaches involve additional scan paths which require considerably more logic. Also, existing pad scan methods do not measure DC threshold and output levels.
The use of level sensitive scan design (LSSD) in the operation and testing of VLSI microcircuits is well-known. See, for example, the article "A Logic Design Structure for LSI Testability" by Eichelberger et al, which appeared in the PROCEEDINGS of the 14th Design Automation Conference, 1977, at pages 462-468.
FIG. 1 illustrates a prior art implementation of LSSD to support efficient testing and maintenance of a microcircuit chip 10. The chip 10 includes VLSI logic which is generally centered in the chip 10 and recessed from its four edges. Input signals are provided to the logic 12 through a plurality of input cells 14. The outputs of the logic 12 are provided through a plurality of output cells 16. Interposed between the input cells and the logic 12 are a plurality of input shift register latches 18 (SRL's). A plurality of output SRL's 12 is provided between the ouput of the chip logic 12 and the output cell 16. The input SRL's 18 are each connected to receive an input signal from a respective one of the input cells 14 for registration of an input signal conducted into the chip 10 through the cell. Once registered in the input SRL, the input signal is provided to the logic 12. The input SRL's 18 are also connected to form a serial-in, parallel-out shift register in which a signal pattern is serially shifted into the input SRL's 18, and then into the logic 12. The output SRL's 20 each receive a respective output signal from the logic 12, register the output signal and provide it to a respective one of the output cells 16 to which the SRL is connected. The output SRL's 20 are also connected to form a shift register that can shift in a plurality of logic signals provided by the logic 12 and then serially shift those signals out. The chip 10 also has a connection between the input SRL's 18 and the output SRL's 20, illustrated by signal path 22, which effectively connects the input and output SRL's to form a single shift register.
In the architecture of the chip 10, an input signal pad 24 is connected by signal path 25 to the serial-in input of the serial shift register comprising the input and output SRL's; the serially-shifted output of the shift register is taken through the signal pad 26, connected through the signal path 27 to the serial output of the register.
As thus described, the shift register comprising the elements 24, 25, 18, 22, 20, 27, and 26, supports, in addition to the function of input and output signal registration, the ability to test the logic 12 just after manufacture of the chip 10. The test procedure involves, first, serially shifting a known signal pattern into the serially-connected input and output SRL's through the input signal pad 24, and observing the output through the signal pad 26. This validates the structure and operation of the input and output SRL's. Next, known patterns of signals are shifted serially into the input SRL's 18 and in parallel therefrom to the logic 12. In response to the successive patterns of signals, the logic 12 generates output signals which are provided to the output SRL's 20. Each set of logic output signals which is parallel loaded into the output SRL's 20 from the logic 12 is serially shifted out through the pad 26. In this manner, virtually all of the operational states of logic 12 can be tested. This technique of testing is referred to as "boundary scanning" because the input and output SRL's are located adjacent the physical and functional boundaries of the logic 12 and are structured to sequentially stimulate the logic 12 with a succession of determinable input signal patterns.
A significant limitation on the prior art implementation of boundary scan testing is that it cannot efficiently and effectively test the input and output cells of a micro circuit such as the chip 10. To understand this limitation, consider the input cell 30, which is representative of all of the plurality of input cells 14, and the output cell 34, representative of all of the output cells 16. Input cell 30 consists of the metalized signal pad 31 which is connected to the signal input of an input buffer located in the area of the chip 10 indicated by reference numeral 32. The output of the input buffer 32 is connected, in turn, to the input SRL 33. As is known, there may be hundreds of input cells, each including a metalized input signal pad having dimensions which prevent signal activation of the pads by, for example, a contact probe. Similarly, the output cell 34 consists of an output buffer 35 having an input and an output, with the output of the buffer 35 being connected to the metalized output signal pad 36. The input of the buffer 35 is connected to the output of a respective SRL 37 of the plurality 20. As with the input cells, the output signal pad of the output cells 16 are too small and too numerous to effectively test by contact signal probing.
While input and output testing of the input cells 14 and output cells 16 can be conducted after the micro circuit chip 10 is mounted in a chip carrier or package having pins through which signals can be inserted or received by conventional carrier means, postponing such testing until this stage of fabrication significantly increases the manufacturing costs of such chips. Now, if input and output testing indicate malfunction of input or output cells, the defective circuit represents a significant cost in fabrication and assembly.
Therefore, an urgent need exists to provide the capability of testing input and output cells after microcircuit fabrication, but prior to the portion of the manufacturing process in which the chips are packaged.